BUS CYCLE

(n.) On the SBus , a series of clock cycles beginning (in the case of a DVMA master ) with a particular master receiving a grant and, in all cases, concluding with the address strobe being unasserted by the SBus controller . For DVMA masters, a bus cycle is divided into two phases: a translation cycle and a slave cycle . However, in the case of a CPU master , the translation cycle does not occur as part of the bus cycle.