ARCHITECTURE

set associative cache single program/multiple data ANSI/SPARC Architecture Extended Industry-Standard Architecture NUXI problem ESA northbridge Core Protocol Stack CAM CA architecture Non-Uniform Memory Access three-tier Joint Test Action Group pipeline break CPU pipeline third generation computer Next Program Counter ISA Byzantine Cache On A STick hit Cellular Neural Network primary cache emulation Adaline Java Virtual Machine PowerPC Platform power save mode prepaging microprocessor central processing unit CNN output segmented address space DAG cognitive architecture bus master Streaming SIMD Extensions -endian hit rate Harvard architecture southbridge 16 bit cellular multiprocessing Industry Standard Architecture stack pointer input address space big-endian distributed memory superscalar Intelligent Input/Output flat address space Moore's Law Axiomatic Architecture Description Language memory address space memory mapped I/O Flynn's taxonomy segment SSE-2 DNA computing 3DNow! Professional Direct Memory Access direct mapped cache 3DNow! Micro Channel Architecture instruction set architecture state instruction set instruction prefetch middle-endian microlog asynchronous asynchronous logic Memory Type Range Registers orthogonal instruction set Task Control Block ping-pong bus systolic array second generation computer fourth generation computer fault tolerance Data Address Generator data bus Lisp Machine fetch-execute cycle little-endian data path 64 bit first generation computer bit slice Dynamic Address Translation main memory Redundant Arrays of Independent Disks Translation Look-aside Buffer 32-bit application BLOB dynamic translation write-through Very Large Memory virtual virtual address wait state von Neumann architecture USB XT bus architecture working set Windows Open Service Architecture wintel VLM